VLSI Design & Technology Test Questions Set - 3

1)   Which among the following EDA tool is available for design simulation?

a. OrCAD
b. ALDEC
c. Simucad
d. VIVElogic
Answer  Explanation  Related Ques

ANSWER: VIVElogic

Explanation:
No explanation is available for this question!


2)   Which among the following functions are performed by MSI category of IC technology?

a. Gates, Op-amps
b. Microprocessor/A/D
c. Filters
d. Memory/DSP
Answer  Explanation  Related Ques

ANSWER: Filters

Explanation:
No explanation is available for this question!


3)   The 'next' statements skip the remaining statement in the ________ iteration of loop and execution starts from first statement of next iteration of loop.

a. Previous
b. Next
c. Current (present)
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Current (present)

Explanation:
No explanation is available for this question!


4)   An Assert is ______ command.

a. Sequential
b. Concurrent
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Both a and b

Explanation:
No explanation is available for this question!


5)   Timing analysis is more efficient with synchronous systems whose maximum operating frequency is evaluated by the _________path delay between consecutive flip-flops.

a. shortest
b. average
c. longest
d. unpredictable
Answer  Explanation  Related Ques

ANSWER: longest

Explanation:
No explanation is available for this question!


6)   What is/are the necessity/ies of Simulation Process in VHDL?

a. Requirement to test designs before implementation & usage
b. Reduction of development time
c. Decrease the time to market
d. All of the above
Answer  Explanation  Related Ques

ANSWER: All of the above

Explanation:
No explanation is available for this question!


7)   Why is the use of mode buffer prohibited in the design process of synthesizer?

a. To avoid mixing of clock edges
b. To prevent the occurrence of glitches & metastability
c. Because critical path has preference in placement

d. Because Maximum ASIC vendors fail to support mode buffer in libraries
Answer  Explanation  Related Ques

ANSWER: Because Maximum ASIC vendors fail to support mode buffer in libraries

Explanation:
No explanation is available for this question!


8)   If a port is declared as buffer, then which problem is generated in hierarchical design due to mapping with port of buffer mode of other entities only?

a. Structural Modeling
b. Functional Modeling
c. Behavioral Modeling
d. Data Flow Modeling
Answer  Explanation  Related Ques

ANSWER: Structural Modeling

Explanation:
No explanation is available for this question!


9)   Which UART component/s divide/s the system clock to provide the bit clock with the period equal to one bit time and Bclock x 8?

a. Baud Rate Generator
b. Transmitter Section
c. Receiver Section
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Baud Rate Generator

Explanation:
No explanation is available for this question!


10)   In Gray coding, when the state machine changes state, ______ bit/s in the state vector changes the value.

a. one
b. two
c. four
d. eight
Answer  Explanation  Related Ques

ANSWER: one

Explanation:
No explanation is available for this question!


11)   Which type of CPLD packaging comprises pins on all four sides that wrap around the edges of chip?

a. Plastic-Leaded Chip Carrier (PLCC)
b. Quad Flat Pack (QFP)
c. Ceramic Pin Grid Array (PGA)
d. Ball Grid Array (BGA)
Answer  Explanation  Related Ques

ANSWER: Plastic-Leaded Chip Carrier (PLCC)

Explanation:
No explanation is available for this question!


12)   An antifuse element initial provides ______ between two conductors in absence of the application of sufficient programming voltage.

a. Conduction
b. Insulation
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Insulation

Explanation:
No explanation is available for this question!


13)   In spartan-3 family architecture, which programmable functional element accepts two 18 bit binary numbers as inputs and computes the product?

a. Configurable Logic Blocks
b. Input Output Blocks
c. Block RAM
d. Multiplier Blocks
Answer  Explanation  Related Ques

ANSWER: Multiplier Blocks

Explanation:
No explanation is available for this question!


14)   Which level of routing resources are supposed to be the dedicated lines allowing output of each tile to connect directly to every input of eight surrounding tiles?

a. Ultra-fast local resources
b. Efficient long-line resources
c. High speed, very long-line resources
d. High performance global networks
Answer  Explanation  Related Ques

ANSWER: Ultra-fast local resources

Explanation:
No explanation is available for this question!


15)   Maze routing is also known as ________

a. Viterbi's algorithm
b. Lee/Moore algorithm
c. Prim's algorithm
d. Quine-McCluskey algorithm
Answer  Explanation  Related Ques

ANSWER: Lee/Moore algorithm

Explanation:
No explanation is available for this question!


16)   Maze routing is used to determine the _______path for a single wire between a set of points, if any path exists.

a. Shortest
b. Average
c. Longest
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Shortest

Explanation:
No explanation is available for this question!


17)   In a chip, which type/s of pad design/s is/are adopted to solve the problem of pin count?

a. Input pad design
b. Output pad design
c. Three state pad design
d. All of the above
Answer  Explanation  Related Ques

ANSWER: Three state pad design

Explanation:
No explanation is available for this question!


18)   The power consumption of static CMOS gates varies with the _____ of power supply voltage.

a. square
b. cube
c. fourth power
d. 1/8 th power
Answer  Explanation  Related Ques

ANSWER: square

Explanation:
No explanation is available for this question!


19)   Which factor/s play/s a crucial role in determining the speed of CMOS logic gate?

a. Load capacitance
b. Supply voltage
c. Gain factor of MOS
d. All of the above
Answer  Explanation  Related Ques

ANSWER: All of the above

Explanation:
No explanation is available for this question!


20)   In high noise margin (NMH), the difference in magnitude between the maximum HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the _________gate.

a. Driven
b. Receiving
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Receiving

Explanation:
No explanation is available for this question!


21)   In CMOS circuits, which type of power dissipation occurs due to switching of transient current and charging & discharging of load capacitance?

a. Static dissipation
b. Dynamic dissipation
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Dynamic dissipation

Explanation:
No explanation is available for this question!


22)   In accordance to the scaling technology, the total delay of the logic circuit depends on ______

a. The capacitor to be charged
b. The voltage through which capacitance must be charged
c. Available current
d. All of the above
Answer  Explanation  Related Ques

ANSWER: All of the above

Explanation:
No explanation is available for this question!


23)   In two-stage op-amp, what is the purpose of compensation circuitry?

a. To provide high gain
b. To lower output resistance & maintain large signal swing
c. To establish proper operating point for each transistor in its quiescent state
d. To achieve stable closed-loop performance
Answer  Explanation  Related Ques

ANSWER: To achieve stable closed-loop performance

Explanation:
No explanation is available for this question!


24)   According to the principle of current mirror, if gate-source potentials of two identical MOS transistors are equal, then the channel currents should be _______

a. Equal
b. Different
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Equal

Explanation:
No explanation is available for this question!


25)   PSSR can be defined as the product of the ratio of change in supply voltage to change in output voltage of op-amp caused by the change in power supply & _______ of op-amp.

a. Open-loop gain
b. Closed-loop gain
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Open-loop gain

Explanation:
No explanation is available for this question!


26)   Which among the following serves as an input stage to most of the op-amps due to its compatibility with IC technology?

a. Differential amplifier
b. Cascode amplifier
c. Operational transconductance amplifiers (OTAs)
d. Voltage operational amplifier
Answer  Explanation  Related Ques

ANSWER: Differential amplifier

Explanation:
No explanation is available for this question!


27)   Which among the following is/are responsible for the occurrence of 'Delay Faults'?

a. Variations in circuit delays & clock skews
b. Improper estimation of on-chip interconnect & routing delays
c. Aging effects & opens in metal lines connecting parallel transistors
d. All of the above
Answer  Explanation  Related Ques

ANSWER: All of the above

Explanation:
No explanation is available for this question!


28)   Due to the limitations of the testers, the functional test is usually performed at speed _______the target speed.

a. Lower than
b. Equal to
c. Greater than
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Lower than

Explanation:
No explanation is available for this question!


29)   High observability indicates that ________number of cycles are required to measure the output node value.

a. More
b. Equal
c. Less
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Less

Explanation:
No explanation is available for this question!


30)   Basically, an observability of an internal circuit node is a degree to which one can observe that node at the _______ of an integrated circuit.

a. Inputs
b. Outputs
c. Both a and b
d. None of the above
Answer  Explanation  Related Ques

ANSWER: Outputs

Explanation:
No explanation is available for this question!